M.Tech in VLSI DESIGN from Indian Institute of Information Technology and Management, Gwalior (CGPA 9.35 ).
B.Tech (Electronics and Communication)Jamia Millia Islamia , New Delhi (CGPA: 7.86).
Currently working as Faculty Associate in Gautam Buddha University, Greater Noida.
Worked as an ASIC Engineer in Soctronics Pvt Ltd Hyderabad.
Awards and Achievements
M.Tech Gold Medalist in VLSI.
Gate Percentile 94.75 Best Paper award in ABV-IIITM paper presentation contest organized by IETE and ABV-IIITM, Gwalior.
Secured 3rd position in Computer Society of India sponsored All India Hardware Design Contest
Area of Interest
Analog Signal Processing
Developed C++ based software for implementation of FIR, IIR digital filters, FFT algorithms, ADC and DAC and Circular convolutions under the guidance of Dr. R.S Anand, I.I.T Roorkee during under graduate Industrial training program.
Designed a high performance low voltage current mirror based on flipped voltage technique.In this Ultra low voltage current mirror is capable of operating at 0.8V with low compliance at input (0.3V) and output (0.2V) for input current of 200uA. The design is verified using Smart Spice and Cadence Virtuoso Layout Editor for 0.13um Technology. The circuit is capable of operating from 4nA to 350uA with a bandwidth of 2.1GHz. Will be published in Journal of Active and Passive Electronic Devices in 2011.
Designed a high performance 0.8V CMOS Opamp Amplifier and verified its functionality using SmartSpice and Cadence Virtuoso Layout Editor. It uses 0.13uM technology with 0.8V supply voltage. Gain of this OTA is compared with existing OTA in research paper and is found to exhibit 105dB gain , 20dB of gain margin and 88o of phase margin, consuming 10.6uW of power.
Ultra Low Voltage Band gap circuit is presented in this paper using FGMOS technique. In this paper we took advantage of threshold voltage tuning of FGMOS to generate multiple references voltages in the range of mV which can be used as references in biomedical applications. Spectre Simulations are carried out in 90nm technology with supply voltage of 1.8V. Main objective of this paper to generate voltage references in mV range using minimum number of MOS as compared to existing topologies.
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