Gate

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity andg is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

y : OUT STD_LOGIC);

end andg;

architecture Behavioral of andg is

begin

Y<=A AND B;</nowiki